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%
%  Rychla reference k zakladum programovaciho jazyka VHDL, 
%  s durazem na syntezu HW
%
%  Martin Bruchanov -- bruxy at regnet dot cz
%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

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\pagestyle{empty}

\begin{document} 
\begin{multicols}{2}
\begin{center}
{\huge \textbf{Programovac� jazyk VHDL}}
\end{center}

Na za��tku p�idat knihovn� podporu:

\begin{verbatim}
    library IEEE;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
\end{verbatim}

\respac
\section{Datov� typy}

Prom�nn� mohou b�t uvnit� PROCESS, FUNCTION
nebo PROCEDURE.\\[2mm] 
VARIABLE jm�no : typ ( := hotnota );

P�i�azen�: 	prom�nn� $:=$ hodnota; sign�l $<=$ hodnota;

\begin{itemize}\itemspace
\item boolean -- True, False
\item integer -- cel� ��sla v rozsahu $-2^{32}$--$2^{32}$; 

Jin� ��seln� soustavy vyj�d�eny pomoc�:

\vspace{-2mm}

\begin{center}
			z�klad soustavy \# hodnota \#
\end{center}

P�.:  \texttt{42} (des�tkov�), \texttt{2\#101010\#},
\texttt{16\#2A\#}

Pro lep�� �itelnost mo�nost odd�lovat \uv{\_}:

\vspace{-2mm}

\begin{verbatim}
	B"1010_1111_1100", 16#A_F_C#
\end{verbatim}

Zad�n� rozsahu datov�ho typu:

\vspace{-2mm}

\begin{verbatim}
	variable state : integer range 0 to 4;
\end{verbatim}


\item natural -- cel� ��sla v rozsahy $0$--$2^32$ 
\item real -- \texttt{2.75}, \texttt{2\#10.11\#}, \texttt{16\#2.C\#}
\item character -- \texttt{'A'}, \texttt{'H'}
\item string -- \texttt{"ahoj vole!"}
\item bit -- \texttt{'0'}, \texttt{'1'}
\item bit\_vector -- \texttt{B"0111011"} (bin.), \texttt{X"3B"}
(hexa.), \texttt{7"73"} (oct.)

\item std\_ulogc, std\_ulogic\_vector
\item std\_logic, std\_logic\_vector -- maj� 
definovanou rezolu�n� funkci p�i setk�n�
dvou hodnot na jednom dr�tu

Dev�tihodnotov� logika:

\vspace{-2mm}

\begin{verbatim}
'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'
\end{verbatim}
\end{itemize}

\subsection{U�ivatelsky definovan� datov� typ}

\begin{verbatim}
TYPE bit IS ('0', '1')
TYPE my_integer IS RANGE -32 TO 32;
\end{verbatim}

\subsection{V��tov� typ}

\texttt{TYPE color IS (red, green, blue);}

\subsection{Pole}

TYPE n�zev IS ARRAY (specifikace) OF datov� typ;

\begin{verbatim}
TYPE matrix IS ARRAY (0 TO 2) 
     OF std_logic_vector(7 downto 0); 

matrix(0)(7 DOWNTO 3) <= "1010"; 
matrix <= ((others => '0'), 
           (others =>'0'), 
           "11110000"); 
\end{verbatim}

\subsection{Sign�ly}

SIGNAL jm�no : typ (:= po��te�n� hodnota);

\begin{verbatim}
SIGNAL bus : std_logic_vector(3 downto 0) 
                                     := "0101";  
SIGNAL bus : std_logic_vector(3 downto 0) 
                          := ('0','1','0','1'); 
\end{verbatim}

\subsection{Agrega�n� oper�tory}
my\_vector : bit\_vector (3 down 0);

\begin{itemize}\itemspace
\item 
	my\_vector(3) $<=$ '1';\\
	my\_vector(2) $<=$ A and B;\\
	my\_vector(1) $<=$ '0';\\
	my\_vector(0) $<=$ A xor B;

	Mo�no napsat nahu�t�n�:

	my\_vector('1', A and B, '0', A xor B);\\

\item
my\_vector'('0', '1', '0', '0'); -- jinak: \\
my\_vector'(3 $=>$ '1', others $=>$ '0');
\end{itemize}

\subsection{Atributy}
\subsubsection{Atributy pol� a vektor�}

\begin{verbatim}
signal c : in bit_vector(7 downto 0) := "10101010";
             std_logic_vector
\end{verbatim}

\begin{itemize}\itemspace
\item c'LOW  = 0  -- nejni��� index pole, 
\item c'HIGH = 7 -- nejvy��� index pole 
\item c'LEFT = 7 -- nejlev�j�� index pole
\item c'RIGHT = 0 -- nejprav�j�� index pole
\item c'RANGE = (7 downto 0) -- rozsah vektoru
\item c'LENGTH = 8 -- vr�t� velikost vektoru
\item c'REVERSE\_RANGE = (0 to 7) -- vr�t� rozsah vektoru v obr�cen�m po�ad�
\end{itemize}

%Atributy v��tov�ch typ�
%
%c'VAL(pozice) -- hodnota na dan� pozici
%c'POS(hodnota) -- pozice spesifikovan� hodnoty
%d'LEFTOF(hodnota) -- hodnota vlevo od specifikovan� hodnoty
%d'VAL(��dek, sloupec) -- hodnota na dan� pozici

\subsubsection{Atributy sign�l�}

\begin{itemize}\itemspace
\item s'EVENT -- pravda pokud se sign�l m�n�
\item s'STABLE -- pravda pokud se sign�l nem�n�
\item s'ACTIVE -- pravda pokud s='1'
%s'QUITE <time> -- pravda pokud nedo�lo ke zm�n� po danou dobu
%s'LAST_EVENT -- vr�t� uplynul� �as od posledn� zm�ny
%s'LAST_ACTIVE --  vr�t� uplynul� �as od posledn� s = '1'
%s'LAST_VALUE -- vr�t� hodnotu p�ed posledn� zm�nou
\end{itemize}

\subsubsection{U�ivatelsk� atributy}

Deklarace: ATRIBUTE n�zev: typ;\\ 
Specifikace: ATRIBUTE n�zev OF c�l: t��da IS hodnota;

\begin{verbatim}
ATRIBUTE number_of_inputs : INTEGER;
ATRIBUTE number_of_inputs OF xor3: SIGNAL IS 3;

inputs <= xor3'number_of_inputs; -- vr�t� hodnotu 3
\end{verbatim}

\subsection{Konstanty}

Mohou b�t definov�ny v deklara�n� ��sti 
ENTITY, ARCHITEKTURE nebo PACKAGE.

CONSTANT n�zev : typ := hodnota;

\subsection{Struktura:}

\tstart
TYPE n�zev IS RECORD\\
\>	a$_1$ : typ ( := hodnota ); \\
\> \>		\ldots \\
\>	a$_n$ : typ ( := hodnota ); \\
END RECORD;
\tstop

\subsection{Konverze datov�ch typ�}

Konverzn� funkce se nach�zej� v bal�ku
\begin{verbatim}
use ieee.std_logic_arith.all;
\end{verbatim}

\begin{itemize}\itemspace
\item conv\_integer(hodnota)
\item conv\_unsigned(hodnota)
\item conv\_signed(hodnota, bit�)
\item conv\_std\_logic\_vector(hodnota, bit�)
\end{itemize}

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

\respac
\section{Priority oper�tor�}

\begin{tabular}{|c||l|}
\hline
		&\qquad\qquad	Stejn�  \\
\hline\hline
Nejvy��� & **, abs, not                    \\
$\downarrow$		 & *, $/$, mod, rem                \\  
$\downarrow$		 & un�rn� $+$ a $-$              \\
$\downarrow$		 & $+$, $-$, \&  (z�et�zen�)       \\
$\downarrow$		 & sll, srl, sla, sra, rol, ror,   \\
$\downarrow$		 & $=$, $/\!\!=$, $<$, $<=$, $>$, $>=$ \\
Nejni��� & and, or, nand, nor, xor, xnor   \\
\hline
\end{tabular}


%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

\respac
\section{Definice entity a jej�ho chov�n�}

\tstart
ENTITY n�zev IS\\
\>	GENERIC (n�zev parametru : typ := hodnota );\\
\>	PORT ( \\
\> \>	port$_1$ : chov�n� typ;\\
\> \>   \ldots\\
\> \>   port$_n$ : chov�n� typ );\\
END n�zev;
\tstop

Nen�-li u parametr� zad�na hodnota, nutno 
zadat p�i vlo�en� komponenty pomoc� GENERIC MAP.
	
Chov�n� port�: IN, OUT, INOUT, BUFFER.

%ENTITY notand IS
%	GENERIC ( parametr : typ := hodnota, \ldots ); -- chyb�-li hodnota, nutno 
%zadat p�i vlo�en� kompomenty pomoc� generic map.
%	PORT (a, b : IN std_logic;
%		  y    : OUT std_logic;
%		  bus  : OUT std_logic_vector( parametr - 1 downto 0);
%		);
%END notand;

\subsection{Vnit�n� popis entity}

ARCHITECTURE definuje chov�n�, entita m��e m�t v�c popis�.

\tstart
ARCHITECTURE n�zev OF entita IS\\
\>	deklara�n� ��st pro komponenty, sign�ly,\ldots\\
BEGIN\\
\>	paraleln� prost�ed�\ldots\\
END n�zev;\\
\tstop

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

\respac
\section{Stavov� p��kazy}

%%%
\tstart
	(label:) \textbf{PROCESS} (citlivostn� seznam)\\
	\>	variable n�zev : typ (rozsah) (:= po��te�n� hodnota);\\
	BEGIN\\
	\> WAIT UNTIL \ldots; $--$ m�sto citl. seznamu \\
	\>	\ldots sekven�n� k�d \ldots\\
    END PROCESS;\\
\tstop

%%%
\tstart
  	(label:) \textbf{WHILE} podm�nka LOOP\\
	\>	\ldots\\
	END LOOP;\\
\tstop
%%%
\tstart
	(label:) \textbf{IF} podm�nka THEN\\
	\>	\ldots\\
	\>	ELSIF podm�nka THEN\\
	\> \>	\ldots\\
	\> ELSE\\
	\> \>	\ldots\\
	END IF;\\
\tstop
%%%
\tstart
	(label:) \textbf{CASE} v�raz IS\\
	\>	WHEN volba$_1$ $=>$ \ldots;\\
	\>	WHEN volba$_2$ $=>$ \ldots;			\\
 	$-${}$-$ chov�n� pro ostatn� volby\\
 	\>	WHEN OTHERS $=>$ \ldots;\\
	END CASE;\\
\tstop

%%%
\tstart
	(label:) \textbf{FOR} i IN rozsah LOOP\\
	\> \ldots\\
	END LOOP;\\
\tstop
	rozsah = { $a$ TO $b$, $b$ DOWNTO $a$, \ldots}
%%%
\tstart
	(label:) \textbf{LOOP}\\
	\>	\ldots\\
	\> EXIT label WHEN podm�nka;\\
	END LOOP;\\
\tstop

\begin{itemize}\itemspace	
\item	\textbf{EXIT} LABEL (WHEN podm�nka); -- bez labelu ukon�� nejbli��� uzav�raj�c� cyklus
\item	\textbf{NEXT} LABEL (WHEN podm�nka); -- sko�� na dal�� iteraci cyklu
\end{itemize}

% IF podm�nka THEN EXIT;
%	end loop;

	

%	clk'event
%	rising_edge(clk)
%	falling_edge(clk)
%

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

\respac
\section{Paraleln� prost�ed�}

\tstart
label: \textbf{FOR} i IN rozsah \textbf{GENERATE}\\
\>	paraleln� p��kaz;\\
END GENERATE;\\
\tstop

\tstart
label: \textbf{IF} podm�nka \textbf{GENERATE}\\
\>	paraleln� p��kaz;\\
END GENERATE;\\
\tstop
		
\subsection{Paraleln� stavov� p��kazy}

\begin{itemize}
\item WHEN (analogie IF):

\tstart
sign�l $<=$ v�raz$_1$ when volby$_1$ else,\\
\>		 v�raz$_2$ when volby$_2$ else,\\
\>		\ldots\\
\>		v�raz$_n$;\\
\tstop

\item WITH (analogie CASE):
\tstart
	WITH testovan� v�raz SELECT\\
	sign�l $<=$ v�raz$_1$ WHEN volby$_1$,\\
	\>		  v�raz$_2$ WHEN volby$_2$,\\
	\>			\ldots\\
	\>		  v�raz$_n$ WHEN OTHERS;\\
	\>	(UNAFFECTED WHEN OTHERS;)\\
\tstop
\end{itemize}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

\respac
\section{Strukturn� popis}

Deklarace komponenty (v deklara�n� ��sti architektury):

\tstart
COMPONENT n�zev\\
\>	( GENERIC \ldots;) $--$ parametry\\
\>	PORT ( \ldots );  $--$ porty\\
END COMPONENT;\\
\tstop

Zapojen�:

\tstart
LABEL:  n�zev komponenty\\
\>	GENERIC MAP ( parametr $=>$ hodnota )  $--$ aktu�ln� parametry\\
\>	PORT MAP ( mapov�n�,\ldots ); $--$ popis struktury\\
\tstop

	Mapov�n�:
	\begin{enumerate}\itemspace
	\item Port komponenty $=>$ port nad�azen� entity 
 	\item Port komponenty $=>$ sign�l architektury
	\item Pozi�n� mapov�n�, nad�azen� sign�ly v po�ad� port� entity
	\end{enumerate}
%		p2 => open (nezapojeno)

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

BLOCK slou�� k seskupov�n� paraleln�ch p��kaz�,
m��e obsahovat lok�ln� deklarace.

\tstart 
label: BLOCK (str�en� sign�l)\\
\>	deklarace\\
BEGIN\\
\>	\ldots\\
END BLOCK label;\\
\tstop

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

\respac
\section{Vlastn� knihovny}

\begin{verbatim}
USE work.n�zev.all;
\end{verbatim}

\tstart
PACKAGE n�zev IS\\
\>	deklarace\ldots \\
END n�zev;
\tstop

\tstart
PACKAGE BODY n�zev IS \\
\> popis funkc� a procedur\ldots \\
END; 
\tstop

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

\respac
\section{Procedury a funkce}

Mohou b�t deklarov�ny uvnit� dekl. ��sti ENTITY,
ARCHITECTURY a PACKAGE.

\tstart
FUNCTION n�zev ( parametr : typ; \ldots)  RETURN typ IS\\
\>	deklarace\\
BEGIN\\
\>	sekven�n� v�razy\\
END n�zev;\\
\tstop

\tstart
PROCEDURE n�zev ( parametr : typ; \ldots) IS\\
BEGIN\\
\>	sekven�n� v�razy\\
END PROCEDURE;\\
\tstop

Parametry procedury mohou b�t IN, OUT nebo INOUT.

\respac
\section{Zpo�d�n� pro simulace}

\begin{itemize}\itemspace
\item	wait for \emph{�as} ns/us/ms/sec; wait on \emph{sign�l} (m�sto
citlivostn�ho seznamu v procesu);  wait
until \emph{v�raz};
\item	y $<=$ NOT (a AND b) AFTER 10 ns; -- definuje setrva�n� zpozd�n�
\item    y $<=$ TRANSPORT b AFTER 10 ns; -- definuje transportn� zpozd�n� 
\end{itemize}
	

\end{multicols}
\end{document}

