library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity clk_divisor is generic (divisor : natural ); port ( CLK_INPUT : in std_logic; RESET : in std_logic; CLK_OUTPUT : out std_logic ); end clk_divisor; architecture Behavioral of clk_divisor is begin DIV: process(CLK_INPUT, RESET) variable c: natural; begin if RESET='1' then c := 0; CLK_OUTPUT <= '0'; elsif CLK_INPUT'event and CLK_INPUT='1' then if c = divisor then CLK_OUTPUT <= '1'; c := 0; else CLK_OUTPUT <= '0'; end if; c := c + 1; end if; end process DIV; end Behavioral;