LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_crc_vhd IS END test_crc_vhd; ARCHITECTURE behavior OF test_crc_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT crc_generic PORT( data : IN std_logic; reset : IN std_logic; ce : IN std_logic; clk : IN std_logic; output : OUT std_logic ); END COMPONENT; --Inputs SIGNAL data : std_logic := '0'; SIGNAL reset : std_logic := '0'; SIGNAL ce : std_logic := '0'; SIGNAL clk : std_logic := '0'; --Outputs SIGNAL output : std_logic; BEGIN -- Instantiate the Unit Under Test (UUT) uut: crc_generic PORT MAP( data => data, reset => reset, ce => ce, clk => clk, output => output ); tb : PROCESS BEGIN reset <= '1'; wait for 100 ns; reset <= '0'; wait for 100 ns; data <= '1'; wait for 100 ns; data <= '0'; wait; -- will wait forever END PROCESS; hodiny : process begin clk <= '1'; wait for 50 ns; clk <= '0'; wait for 100 ns; end process; enable : process begin ce <= '1'; wait; end process; END;