library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity shift_reg is generic ( size : natural ); port ( CLK, RESET, CE : in std_logic; SERIAL_IN : in std_logic; SERIAL_OUT : out std_logic; PARALEL_OUT : out std_logic_vector(size - 1 downto 0) ); end shift_reg; architecture Behavioral of shift_reg is begin Shifter: process(CLK, RESET) variable value : std_logic_vector(size - 1 downto 0) := (others => '0'); variable bit_out : std_logic; begin if RESET = '1' then bit_out := '0'; value := (others => '0'); elsif CLK = '1' and CLK'event then if CE = '1' then bit_out := value(size - 1); value := value(size - 2 downto 0) & SERIAL_IN; end if; end if; PARALEL_OUT <= value; SERIAL_OUT <= bit_out; end process; end Behavioral;